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2-mbit (128k x 16) static ram cy62136cv30 mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05199 rev. *e revised july 19, 2006 features ? very high speed ?55 ns ? voltage range ? 2.7v ? 3.3v ? pin-compatible with the cy62136v ? ultra-low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 7 ma @ f = f max (55 ns speed) ? low standby power ? easy memory expansion with ce and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free 48-ball vfbga package functional description [1] the cy62136cv30 is high-performance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption by 80% when addresses are not toggling. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low, and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 128k x 16 ram array i/o 0 ?i/o 7 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe i/o 8 ?i/o 15 ce we ble bhe a 16 row decoder a 7 a 6 a 3 a 0 a 2 a 1 a 5 a 4 a 8 a 9 a 10 [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 2 of 12 pin configuration [3, 4] product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) f = 1 mhz f = f max v cc(min.) v cc(typ.) [2] v cc(max.) typ. [2] max. typ. [2] max. typ. [2] max. cy62136cv30ll 2.7 3.0 3.3 55 1.5 3 7 15 2 10 70 1.5 3 5.5 12 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h 48-ball vfbga a 16 dnu v cc nc notes: 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. 3. nc pins are not connected to the die. 4. e3 (dnu) pin have to be left floating or tied to v ss to ensure proper operation. top view [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential?0.5v to v cc(max) + 0.5v dc voltage applied to outputs in high-z state [5] ....................................?0.5v to v cc + 0.3v dc input voltage [5] ................................ ?0.5v to v cc + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range device range ambient temperature v cc cy62136cv30 industrial ?40c to +85c 2.7v to 3.3v electrical characteristics over the operating range parameter description test conditions cy62136cv30-55 cy62136cv30-70 unit min. typ. [2] max. min. typ. [2] max. v oh output high voltage i oh = ?1.0 ma v cc = 2.7v 2.4 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v i out = 0 ma cmos levels 7 15 5.5 12 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f = 0 (oe , we , bhe , and ble ) 2 10 2 10 a i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.3v 2 10 2 10 a capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ.) 6 pf c out output capacitance 8 pf thermal resistance [7] parameter description test conditions vfbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board 55 c/w jc thermal resistance (junction to case) 16 c/w notes: 5. v il(min.) = ?2.0v for pulse durations less than 20 ns. 6. tested initially and after any design or process changes that may affect these parameters. 7. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 4 of 12 ac test loads and waveforms parameters 3.0v unit r1 1105 ? r2 1550 ? r th 645 ? v th 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [2] max. unit v dr v cc for data retention 1.5 v cc(max) v i ccdr data retention current v cc = 1.5v, ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 1 6 a t cdr [7] chip deselect to data retention time 0 ns t r [7] operation recovery time t rc ns data retention waveform v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: the venin equivalent all input pulses r th r1 rise time: 1 v/ns fall time: 1 v/ns v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce v cc [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 5 of 12 switching characteristics over the operating range [8] parameter description 55 ns 70 ns unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low-z [9] 5 5 ns t hzoe oe high to high-z [9, 10] 20 25 ns t lzce ce low to low-z [9] 10 10 ns t hzce ce high to high-z [9, 10] 20 25 ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 55 70 ns t dbe bhe /ble low to data valid 25 35 ns t lzbe bhe /ble low to low-z [9] 5 5 ns t hzbe bhe /ble high to high-z [9, 10] 20 25 ns write cycle [11] t wc write cycle time 55 70 ns t sce ce low to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 40 45 ns t bw bhe /ble pulse width 50 60 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [9, 10] 20 25 ns t lzwe we high to low-z [9] 10 10 ns notes: 8. test conditions assume signal transition time of 5 ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30 pf load capacitance. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. it hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 11. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write. [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 6 of 12 switching waveforms read cycle no. 1(address transition controlled) [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce = v il , bhe , ble = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce , bhe , ble transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance t hzoe t hzce t pd t hzbe t lzoe t do e t lzoe t dbe impedance high i cc i sb data out oe ce v cc supply current bhe /ble address [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 7 of 12 write cycle no. 1 (we controlled) [11, 15, 16] write cycle no. 2 (ce controlled) [11, 15, 16] notes: 15. data i/o is high-impedance if oe = v ih 16. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 17. during this period, the i/os are in output state and input signals should not be applied. switching waveforms t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid note 17 t bw data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc data in valid note 17 t bw t sa t hzoe ce address we data i/o oe bhe /ble [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 8 of 12 write cycle no. 3 (we controlled, oe low) [16] write cycle no. 4 (bhe /ble controlled, oe low) [16] switching waveforms t hd sd t ha data in valid t lzwe t sa t aw t hzwe note 17 t bw t wc ce address we data i/o bhe /ble t t pwe t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid t bw note 17 ce address we data i/o bhe /ble t pwe [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 9 of 12 typical dc and ac parameters 12.0 10.0 6.0 4.0 2.7 0 8.0 supply voltage (v) 3.6 2.0 3.3 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) standby current vs. supply voltage supply voltage (v) mobl 2.0 2.7 3.3 50 30 20 10 supply voltage (v) access time vs. supply voltage 0 40 t aa (ns) 60 3.0 2.7 3.3 mobl operating current vs. supply voltage mobl (typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c) 50 30 20 10 2.7 3.6 supply voltage (v) 0 40 t aa (ns) 60 3.3 mobl i sb ( a) 12.0 10.0 6.0 4.0 2.0 2.7 3.6 0.0 8.0 i cc (ma) supply voltage (v) 14.0 3.3 mobl (f = 1 mhz) (f = f max , 70 ns) (f = f max , 55 ns) 12.0 10.0 6.0 4.0 2.0 2.7 3.3 0.0 8.0 i cc (ma) supply voltage (v) mobl (f = 1 mhz) 14.0 3.0 (f = f max , 70 ns) (f = f max , 55 ns) 3.0 3.0 3.0 [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 10 of 12 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power-down standby (i sb ) l x x h h high-z output disabled active (i cc ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l high z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 55 cy62136cv30ll-55bvi 51-85150 48-ball fine pitch bga (6 x 8 x 1 mm) industrial 70 cy62136cv30ll-70bvxi 48-ball fine pitch bga (6 x 8 x 1 mm) pb-free please contact your local cypress sales r epresentative for availability of these parts [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark and more battery life is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
cy62136cv30 mobl ? document #: 38-05199 rev. *e page 12 of 12 document history page document title: cy62136cv30 2-mbit (128k x 16) static ram document number: 38-05199 rev. ecn no. issue date orig. of change description of change ** 112379 02/19/02 gav new data sheet (advance information) *a 114023 04/25/02 jui added bv package diagram changed advance information to preliminary *b 117063 07/12/02 mgn changed preliminary to final *c 118121 08/26/02 mgn added new part numbers: cy 62136cv with wider voltage (2.7v ? 3.6v); cy62136cv33 narrower voltage range (3.0v ? 3.6v) for t aa = 55 ns, improved t pwe min from 45 ns to 40 ns for t aa = 70 ns, improved t pwe min from 50 ns to 45 ns for t aa = 70 ns, improved t lzwe min from 5 ns to 10 ns *d 118622 10/3/02 mgn improved typ. i cc spec. to 7 ma (for 55 ns) and 5.5 ma (for 70 ns) improved max i cc spec. to 15 ma (for 55 ns) and 12 ma (for 70 ns) for t aa = 55 ns, improved t lzwe min. from 5 ns to 10 ns changed upper spec. for supply voltage to ground potential to v cc(max) + 0.5v changed upper spec. for dc voltage applied to outputs in high-z state and dc input voltage to v cc + 0.3v *e 486789 see ecn vkn changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? removed part numbers: cy62136cv and cy62136cv33 updated ordering information table [+] feedback [+] feedback

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